PPC BAT register handling fixed (Technically not emulation bug but OS bug, PPC documentation says '. Automatically update accelerator board ROM settings when board type is changed in GUI. (Original non-flash based boards had separate ROM chip for boot and diag ROMs and boot was only installed if CPU was 68060) Added full CyberStorm MK1 image ($F00000 ROM code is 68060-only), added another 68040 compatible ROM that simulates boards with boot rom jumper disabled or boot rom chip removed. Accelerator board ROM select menus didn't select anything. RTD instruction was set as 68000 compatible (should be 68010+). 68000 + no cycle exact and no 'more compatible' used wrong memory access method. 6800 variants have different (and incompatible) flash rom contents. Blizzard PPC rom name renamed to blizzardppc_060.rom and added blizzardppc_040.rom. Note that this is impossible config, there is no way to have any Z3 boards with BPPC in real world. Never use normal Z3 autoconfig mapping if Blizzard board is emulated to reduce address space conflicts with Blizzard RAM mirror at 0x48000000.

P5_AMIGA_RESET CSMK3/CSPPC/BPPC bit can be only changed if P5_SELF_RESET is cleared first.

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